Conventional methods for forming a semiconductor device isolating barrier include a LOCOS (Local Oxidation of Silicon) method using a nitride layer and an STI (Shallow trench isolation) method which isolates devices by forming a trench on a surface of the semiconductor substrate.
Since the LOCOS method employs a simple process of thermal oxidization of a semiconductor substrate using a nitride layer as a mask, element stress of the oxide layer is small and the generated oxide layer has high quality. However, the device isolating region occupies a large area, thereby limiting the miniaturization of the semiconductor device. On the contrary, in the STI method, after a trench is formed on a surface of a semiconductor substrate, the trench is filled with an insulating film which is subsequently flattened. Accordingly, the STI method creates a small device isolating region, thereby having an advantage with respect to miniaturization of the semiconductor device.
FIGS. 1A to 1F are cross-sectional views showing a conventional insolating method in which a trench is formed on a surface of a semiconductor substrate. As shown in FIG. 1A, after a pad oxide layer 2 having a thickness of about 150 Å is formed on a semiconductor substrate 1, a nitride layer 3 having a thickness of about 2000 Å is formed on the pad oxide layer 2. After a photoresist layer 4 is coated on the nitride layer 3, the photoresist layer 4 is exposed and developed to form a mask to create a trench, (i.e., a device isolating region), on a surface of the semiconductor substrate 1.
As shown in FIG. 1B, a trench T, (i.e., a device isolating region), is formed by etching the semiconductor substrate 1 to a depth of about 3000 Å to about 7000 Å and a width of about 300 Å to about 500 Å after etching the portions of the nitride layer 3 and the pad oxide layer 2 exposed through developing of the photoresist layer 4.
Referring to FIG. 1C, the trench T is filled by depositing a thick insulating layer 6, (i.e., an oxide layer), on a surface of the semiconductor substrate 1 by performing a CVD (chemical vapor deposition) process. Prior to performing the CVD process, a liner oxide layer 5 is formed inside the trench T such that the trench T makes good contact with the filling oxide layer 6 in the process of filling the trench with the insulating layer 6 and such that an edge of the trench is rounded.
Referring to FIG. 1D, after coating the insulating layer 6 with a photoresist layer 7, the photoresist layer 7 is exposed and developed by using a mask. As a result, the photoresist layer pattern 7 remains only on the insulating layer 6 above the trench T. An insulating layer pattern 6a is formed by etching the insulating layer 6 using the photoresist layer pattern 7 as a mask.
As shown in FIG. 1E, after removing the photoresist layer pattern 7, a device isolating barrier 8, (i.e., flattened insulating layer pattern 6a), is formed by polishing and flattening the insulating layer pattern 6a to the height of the nitride layer 3 through a CMP (chemical mechanical polishing) process.
As shown in FIG. 1F, when the exposed nitride layer 3 is removed by wet etching using phosphoric acid, the semiconductor substrate 1 is divided into active regions at both sides of the device isolating barrier 8 and a device isolating region corresponding to the device isolating barrier 8.
In the conventional semiconductor device isolating method, the oxide layer and the nitride layer 3 are flattened, and then the exposed nitride layer 3 is removed by phosphoric acid. During the flattening of layers, an electric field is concentrated on a periphery A of the trench T, as shown in FIG. 1F, thereby causing the Kink effect, (i.e., leakage current generation at the trench T), which deteriorates the reliability and characteristics of the semiconductor device.
Although not shown in the drawings, after a gate electrode including a conducting layer is formed on the active region by using a general gate electrode forming method, drain/source regions are formed employing the gate electrode as a criterion by executing impurity ion implantation.
In this case, a problem occurs in that a device isolation resistance is changed since impurities are also doped inside the trench during the impurity ion implantation to form the drain/source regions.